What You'll Do
• Working directly with ASIC and System design teams to evaluate design tradeoffs and optimize design performance / risk / cost / manufacturability
• Drive next generation Serdes IP characterization and ASIC/system feasibility studies
• Perform pre- and post-route signal integrity analysis of both PCB and ASIC package designs for both Serial bus and Parallel bus
• Modeling and analyzing power delivery networks
• Performing physical measurements for design validation and simulation correlations
• Driving methodology enhancements and automation, improving performance and efficiency
• Develop simulation tools with EDA vendor(s) whenever needed for analysis.
• Mentor junior engineers and interns
Who You'll Work With
SI team is seeking a signal integrity engineer for design and analysis of high speed interfaces and power distribution network. The candidate will participate in the definition and design of current and next generation ASIC, package, printed circuit board (PCB), and system interconnect. The individual will be the key person to work closely with system architects, ASIC engineers, CAD engineers in creation of next generation high performance networking products.
Who You Are
Must have skills/experiences
• Self-motivation, Strong teamwork, Strong communication skills and Out of the box thinking with the strong desire to innovate are essential.
• Ability to define a project schedule and requirements, then deliver to that schedule
• Good English.
Good to have skills/experiences
• In depth understanding of electromagnetic theory is required
• Knowledge of Serial and Parallel Bus simulation methodology
• Strong lab skills and measurement experience are required (VNA, TDR, Scope, BERT)
• Strong tools knowledge (HFSS, CST, ADS, HSpice, SiSoft QCD and QSI, Cadence PowerSI/DC, Allegro)
Plus to have skills/experiences
• Working knowledge of system level power integrity and budgeting (DC, AC, transient analysis)
• Hands on experience with ASIC development focused on Serdes, DDR4 and IO IP selection, package design and simulation, ASIC level power integrity
• Working experience with high speed NRZ and PAM4 Serdes, PLLs, CDR and FEC
• Hands on experience with script knowledge(Python, Matlab etc)
PhD/MSEE combined with 1+ years of related experience, or BSEE combined with 3+ yrs related experience.